The background description includes information that may be useful in understanding present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the sequence of past inputs, the input history. This is in contrast to combinational logic, whose output is a function of only the present input. That is, sequential logic has state (memory) while combinational logic does not. As conventionally known, Shift Register (SR) is a type of sequential logic circuit that can be used for storage or transfer of data in the form of binary numbers. This sequential device loads data present on its inputs and then moves or “shifts” it to its output once every clock cycle, hence the name Shift Register. A shift register basically consists of several single bit “D-Type Data Storage elements”, one for each data bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement so that the output from one data storage element becomes the input of the next storage element, and so on.
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output of each flip-flop is connected to the ‘data’ input of the next flip-flop in the chain, resulting in a circuit that shifts by one position the ‘bit array’ stored in it, ‘shifting in’ the data present at its input and ‘shifting out’ the last bit in the array, at each transition of the clock input. Data bits may be fed in or out of a shift register serially, that is one after the other from either the left or the right direction, or all together at the same time in a parallel configuration. The number of individual data storage elements required to make up a single Shift Register device is usually determined by the number of bits to be stored with the most common being 8-bits (one byte) wide constructed from eight individual data storage elements. Shift Registers are used for data storage or for the movement of data and are therefore commonly used inside calculators or computers to store data such as two binary numbers before they are added together, or to convert the data from either a serial to parallel or parallel to serial format. The individual data storage elements that make up a single shift register are all driven by a common clock signal making them synchronous devices.
The directional movement of the data through a shift register can be either to the left (left shifting) to the right (right shifting) left-in but right-out (rotation) or both left and right shifting within the same register thereby making it bidirectional. FIG. 1A illustrates an exemplary working 100 of shift register as available in the prior-art. The effect of data movement from left to right through a shift register can be presented graphically in FIG. 1A. Also, the directional movement of the data through a shift register can be either to the left (left shifting) to the right (right shifting) left-in but right-out (rotation) or both left and right shifting within the same register thereby making it bidirectional. However, because data must be retrieved one bit at time, it also takes N clocks to retrieve N bits of data stored in an N-bit SISO shift register. The 4-bit shift register requires 4 clocks to retrieve the 4 bits stored in it. Thus, the conventional SRs need to be made configurable and re-configurable such that they are more precise in data storage and transfer of the data and meet the requirement of real time dynamic nature of operations.
Conventionally known, programmable logic device (PLD) is an electronic component used to build reconfigurable digital circuits. The PLD is any IC that has programmable functions and programmable interconnections. PLD commonly includes one or more data paths, or collections of digital signals routed through the system during processing. The size of a collection, called the “data width” or “data path width” herein, depends on a number of factors. One factor in determining the data path width is the significance of the signals (i.e., the information that the signals represent, and the format of the signals). Another factor is the required speed of operation of the design. Yet another factor is the size constraints introduced by the design. Other factors may also possibly affect the data path width. In some cases, it may be desirable to modify the width of a data path at some point in the design, changing the extent to which data is propagated in parallel. This may be necessary, for example, because of different operating speeds in different portions of the design, or different constraints on the data width in different portions of the design. It may also be beneficial for this data width modification to be programmable and to be done dynamically. It would therefore be desirable to have a PLD capable of implementing a variable-width data path.
There is therefore a need in the art to provide a new, cost-effective, technically advanced and improved system, device and method that enables to not only efficiently reduce the number of flops but also to reduce the latency associated while reducing the number of flops. Further, there is also a need to provide improved system, device and method that includes storage capable of ensuring that all combinations of bits fits in the storage without any left over.
All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.